1. Field of the Invention
The present invention relates to a liquid crystal display panel, and more particularly, to a power supply for a liquid crystal display panel supplying a common voltage and a gamma reference voltage by using one integrated circuit (IC) chip and having a gate on/off voltage generating unit.
2. Description of the Related Art
In general, a liquid crystal display panel displays a picture on a screen by adjusting light transmittance of a liquid crystal according to picture information. The liquid crystal display panel includes liquid crystal cells arranged in a matrix form and a switching device such as a TFT (thin film transistor) corresponding to the liquid crystal cells to switch picture information supplied to each liquid crystal cell.
A driving unit of the liquid crystal display panel controls the switching device to supply the picture information to the corresponding liquid crystal cells. In addition, the driving unit of the liquid crystal display panel controls picture information so as to have positive and negative electricity within a specific voltage level in order to restrain picture deterioration such as flickering or an afterimage, and lower a driving voltage.
In general the liquid crystal display panel has gamma characteristics wherein gradation of a picture is varied nonlinearly according to a voltage level of picture information. The gamma characteristics are caused by light transmittance of liquid crystal. Light transmittance of the liquid crystal is not linearly varied according to a voltage level of picture information, and gradation of a picture is not linearly varied according to light transmittance of the liquid crystal. Accordingly, in order to vary the gradation of the picture according to a voltage level of picture information, by applying a preset gamma voltage to the voltage level of the picture information as an offset voltage, the gamma characteristics can be compensated and deterioration of the picture can be prevented.
In order to generate a driving voltage for controlling the switching device, a common voltage having a specific voltage level and a gamma voltage for compensating the gamma characteristics, voltage generating circuits are disposed in the liquid crystal display panel, and are described with reference to the accompanying drawings.
FIG. 1 is a schematic view of a block construction of a liquid crystal display panel and a driving unit thereof according to the related art. In FIG. 1, a liquid crystal display apparatus includes a liquid display panel 10 having a picture display unit 13, a gate driving unit 20, and a data driving unit 30, a timing controller 40 for controlling a driving timing of the gate driving unit 20 and the data driving unit 30, and a power unit 50 for supplying a voltage to the liquid crystal display panel 10, the gate driving unit 20, the data driving unit 30, and the timing controller 40 by receiving a 3.3V system voltage (VSYS).
In the picture display unit 13 of the liquid crystal display panel 10, liquid crystal cells are arranged on a region at which gate wiring placed in the horizontal direction at regular intervals and data wiring placed in the vertical direction at regular intervals cross each other. In addition, the gate driving unit 20 of the liquid crystal display panel 10 drives the liquid crystal cells arranged in a matrix form by the gate wiring units by sequentially applying scanning signals to the gate wiring, and the data driving unit 30 applies picture information to the liquid crystal cells operated according to the scanning signals received through the data wiring.
The timing controller 40 supplies a control signal (CS) to the gate driving unit 20 and supplies the control signal (CS) and picture information (DATA [R,G,B]) to the data driving unit 30. The timing controller 40 controls a timing operation of the gate driving unit 20 and the data driving unit 30 by supplying a certain clock signal, a gate start signal, and a timing signal as the control signal (CS).
The power unit 50 includes a gate driving voltage generating unit 51 for supplying gate on/off voltages (VG-ON, VG-OFF) to the gate driving unit 20; a common voltage generating unit 52 for supplying a common voltage (Vcom) to a common electrode (not shown) of the picture display unit 13; and a gamma voltage generating unit 53 supplying a gamma voltage (VGMA) for compensating the gamma characteristics to the data driving unit 30.
FIG. 2 is a circuit diagram of a gate driving voltage generating unit of FIG. 1. In FIG. 2, the gate driving voltage generating unit 51 includes a booster 61 for generating a reference voltage (VREF) of 7V by boosting the 3.3V system voltage (VSYS), and a first and a second pumping units 62, 63 for generating the gate on/off voltages (VG-ON, VG-OFF) by pumping and clamping the reference voltage (VREF) of the booster 61. The booster 61 includes an 11th node (N11) in which the 3.3V system voltage (VSYS) is applied and an 11th capacitor (C11) contacted to an earth potential (VSS) therebetween, a 12th node (N12) in which the earth potential (VSS) is periodically applied by the switching device (SW) and an 11th inductor (L11) contacted to the 11th node (N11) therebetween, a 13th node (N13) in which a forward 11th diode (D11) is contacted to the 12th node (N12) therebetween, a 12th capacitor (C12) contacted to the earth potential (VSS) therebetween, an 11th and a 12th resistance (R11, R12) contacted to the earth potential (VSS) therebetween in order to boost the 3.3V system voltage (VSYS) to the 7V reference voltage (VREF) and outputting it.
The first pumping unit 62 includes a 21st node (N21) in which a 21st capacitor (C21) is contacted to the 12th node (N12) therebetween, and a forward 21st diode (D21) is contacted to the 13th node (N13) of the booster 61 therebetween, a 22nd node (N22) in which a 22nd capacitor (C22) is contacted to the 13th node (N13) of the booster 61 therebetween, and a forward 22nd diode (D22) is contacted to the 21st node (N21) therebetween, a 23rd node (N23) in which a 23rd capacitor (C23) is contacted to the 12th node (N12) of the booster 61 therebetween, and a forward 23rd diode (D23) is contacted to the 22nd node (N22) therebetween, and a 24th node (N24) in which a forward 24th diode (D24) is contacted to the 23rd node (N23) therebetween, and a 24th capacitor (C24) is contacted to the earth potential (VSS) therebetween to output a 21V gate ON voltage (VG-ON) by pumping and clamping the 7V reference voltage (VREF).
The second pumping unit 63 includes a 31st node (N31) in which a 31st capacitor (C31) contacted to the 12th node (N12) of the booster 61 therebetween and a backward 31st diode (D31) contacted to the earth potential (VSS) therebetween; and a 32nd node (N32) in which a backward 32nd diode (D32) is contacted to the 31st node (N31) therebetween and a 32nd capacitor (C32) contacted to the earth potential (VSS) therebetween to output a −7V gate OFF voltage (VG-OFF) by pumping and clamping the 7V reference voltage (VREF).
FIG. 3 is a circuit diagram of a circuit construction of a common voltage generating unit of FIG. 1. In FIG. 3, the common voltage generating unit 52 includes a 41st and a 42nd resistance (R41, R42) for dividing a power voltage (VDD), a variable resistance (VR41) and a 41st capacitor (C41) contacted between the 41st and 42nd resistance (R41, R42) and adjusting a level of the divided power voltage (VDD), and a 41st operational amplifier (OP-AMP41) receiving the power Voltage (VDD) divided by the 41st and 42nd resistance (R41, R42) and level-adjusted by the variable resistance (VR41) and the 41st capacitor (C41) through a non-inversion terminal (+), receiving back an output thereof through an inversion terminal (−), adjusting a level through the 43 rd resistance (R43) and the 42nd capacitor (C42) and outputting it as the common voltage (Vcom). The 41st and 42nd resistance (R41, R42) generate a specific level common voltage (Vcom) by dividing the power voltage (VDD) and applying it to the non-inversion terminal (+) of the 41st operational amplifier (OP-AMP41). In order to vary the level of the common voltage (Vcom), a resistance value of the variable resistance (VR41) is varied.
FIG. 4 is a circuit diagram of a circuit construction of a gamma voltage generating unit of FIG. 1. In FIG. 4, the gamma voltage generating unit 53 includes a high level unit 71 for generating high level gamma voltage (VGMAH1˜VGMAH5) having an inverted electricity per 1 horizontal cycle (1 Hs) according to dot inversion driving; and a low level unit 72 for generating low level gamma voltage (VGMAL1˜VGMAL5). The high level unit 71 divides the power voltage (VDD51) according to a resistance ratio of the serially contacted 51st˜56th resistance (R51˜R56) and generates the high level gamma voltage (VGMAH1˜VGMAH5) in the 51st˜55th nodes (N51˜N55). The high level gamma voltage (VGMAH1) of the 51st node (N51) has a voltage level corresponding to a black level, the high level gamma voltage (VGMAH3) of the 53rd node (N53) has a voltage level corresponding to an intermediate level, and the high level gamma voltage (VGMAH5) of the 55th node (N55) has a voltage level corresponding to a white level. From the high level gamma voltage (VGMAH1) of the 51st node (N51) to the high level gamma voltage (VGMAH5) of the 55th node (N55), the voltage level is decreased.
In addition, the low level unit 72 divides the power voltage (VDD52) according to a resistance ratio of the serially contacted 57th˜62nd resistance (R57˜R62) and respectively generates the low level gamma voltage (VGMAL1˜VGMAL5) in the 56th˜60th nodes (N56˜N60). The low level gamma voltage (VGMAL1) of the 56th node (N56) has a voltage level corresponding to a black level, the low level gamma voltage (VGMAL3) of the 58th node (N58) has a voltage level corresponding to an intermediate level, and the low level gamma voltage (VGMAL5) of the 60th node (N60) has a voltage level corresponding to a white level. From the low level gamma voltage (VGMAL1) of the 56th node (N56) to the low level gamma voltage (VGMAL5) of the 60th node (N60), the voltage level is increased.
The high level gamma voltage (VGMAH1˜VGMAH5) and the low level gamma voltage (VGMAL1˜VGMAL5) are respectively applied to the non-inversion terminal (+) of the 51st˜the 60th operational amplifiers (OP-AMP51˜OP-AMP60) through a bus line. The output of the 51st˜the 60th operational amplifiers (OP-AMP51˜OP-AMP60) is returned to the inversion terminal (−) and is outputted to the data driving unit 30 as the gamma voltage (VGMA1˜VGMA10) through the 51st˜the 60th capacitors (C51˜C60) respectively disposed in the output end of the 51st˜the 60th operational amplifiers (OP-AMP51˜OP-AMP60).
As described above, in the power supply of the related art liquid crystal display panel, the gate on/off voltage, the common voltage and the gamma reference voltage generating circuit required for operation of the liquid crystal display panel are separately constructed. Accordingly, since three or four IC chips and additional parts are required, it is difficult to lower production costs and maintain competitive prices.